BEGIN:VCALENDAR VERSION:2.0 PRODID:-//PYVOBJECT//NONSGML Version 1//EN BEGIN:VTIMEZONE TZID:Europe/Brussels BEGIN:STANDARD DTSTART:20001029T030000 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=10 TZNAME:CET TZOFFSETFROM:+0200 TZOFFSETTO:+0100 END:STANDARD BEGIN:DAYLIGHT DTSTART:20000326T020000 RRULE:FREQ=YEARLY;BYDAY=-1SU;BYMONTH=3 TZNAME:CEST TZOFFSETFROM:+0100 TZOFFSETTO:+0200 END:DAYLIGHT END:VTIMEZONE BEGIN:VEVENT UID:20260527T111848Z - 75717@eupp208 DTSTART;TZID=Europe/Brussels:20260416T170000 DTEND;TZID=Europe/Brussels:20260416T174500 CREATED:20260527T111848Z DESCRIPTION:Closin g the Gap Between PIC Designers and Foundries: DRC in PIC Design\nMiss ed the webinar? Watch Now As the photonic integrated circuit (PIC) industr y advances toward large-scale integration\, robust Design Rule Checking (D RC) has become essential for a successful tape-out. Yet for many PIC desig ners\, this final step in the design flow is often the most time-consuming and frustrating. Unexpected last-minute issues\, repeated back-and-forth communication with foundries\, and multiple revision cycles can delay proj ects\, increase costs\, and create unnecessary stress\, ultimately extendi ng time to market. Ensuring that a design is reliable and ready for tape-o ut the first time helps prevent costly iterations and keeps projects on tr ack. Join us for a webinar where we will demonstrate our brand-new product \, Luceda DRC\, a powerful solution that bridges the gap between foundry r equirements and design intent. Luceda DRC enables you to identify and reso lve design rule violations directly in the same environment where you desi gn your PICs and validate your designs against foundry rules. Luceda’s n ative DRC engine integrates design and verification in a single workflow\, helping you detect and resolve violations early\, ensure reliable\, found ry-compliant PIC designs\, and move toward successful tape-outs with confi dence. In this webinar\, you will learn how to: Speaker Toon Snauwaert App lication Engineer at Luceda Photonics ​​​​​​​​​​ Run r ule decks with Luceda’s DRC engine and validate designs against foundry rules.Identify and resolve common PIC design errors early in the design pr ocess.Select different rule groups\, run density checks\, and easily scan through violations in the Luceda Layout Visualizer.Run DRC and visualize v iolations in a different tool\, even without an IPKISS license. Register n ow to deepen your understanding of DRC in PIC design\, learn more about th e Luceda DRC\, and see how Luceda enables you to create tape-out-ready PIC s with [...] DTSTAMP:20260527T111848Z LOCATION:Online event SUMMARY:Closing the Gap Between PIC Designers and Foundries: DRC in PIC Des ign X-ALT-DESC;FMTTYPE=text/html:Closing the Gap Between PIC Designers and Foundries: DRC in PIC Design\nMissed the webinar? Watch Now As the photonic integrated circ uit (PIC) industry advances toward large-scale integration\, robust Design Rule Checking (DRC) has become essential for a successful tape-out. Yet f or many PIC designers\, this final step in the design flow is often the mo st time-consuming and frustrating. Unexpected last-minute issues\, repeate d back-and-forth communication with foundries\, and multiple revision cycl es can delay projects\, increase costs\, and create unnecessary stress\, u ltimately extending time to market. Ensuring that a design is reliable and ready for tape-out the first time helps prevent costly iterations and kee ps projects on track. Join us for a webinar where we will demonstrate our brand-new product\, Luceda DRC\, a powerful solution that bridges the gap between foundry requirements and design intent. Luceda DRC enables you to identify and resolve design rule violations directly in the same environme nt where you design your PICs and validate your designs against foundry ru les. Luceda’s native DRC engine integrates design and verification in a single workflow\, helping you detect and resolve violations early\, ensure reliable\, foundry-compliant PIC designs\, and move toward successful tap e-outs with confidence. In this webinar\, you will learn how to: Speaker T oon Snauwaert Application Engineer at Luceda Photonics ​​​​​​ ​​​​ Run rule decks with Luceda’s DRC engine and validate design s against foundry rules.Identify and resolve common PIC design errors earl y in the design process.Select different rule groups\, run density checks\ , and easily scan through violations in the Luceda Layout Visualizer.Run D RC and visualize violations in a different tool\, even without an IPKISS l icense. Register now to deepen your understanding of DRC in PIC design\, l earn more about the Luceda DRC\, and see how Luceda enables you to create tape-out-ready PICs with [...] END:VEVENT END:VCALENDAR